Very-Large-Scale Integration (VLSI) is the process of creating integrated circuits by combining thousands of transistor-based circuits into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. Currently, as a result of VLSI design techniques, billion-transistor processors are commercially available, an example of which is Intel's Montecito Itanium Chip. Such large systems are expected to become more common as semiconductor fabrication moves from the current generation of 65 nm processors to the next 45 nm generation.
Due to the high complexity and size of current VLSI circuits and chips, present approaches employ a number of different computer tools throughout the VLSI design process. Such tools typically range from silicon layout editors, schematic capture tools and logical generators to logical optimizers and digital simulators. While not every tool may be used in the creation of every design, it is likely that a large subset will, and it is the combination of such tools that causes a large number of problems.
More particularly, while a given tool may be adapted to running on one machine architecture, another tool might only run on a different machine. This means that a designer must log in to the correct machine at each stage before running the associated tool. Moreover, as a design is processed, it must be passed from tool to tool. The designer may use a schematic capture tool for initial input, then desire that the design be minimized and finally simulated. However, nearly every tool inspects its input and produces its output in a unique format. All of this requires a large amount of time and effort in the design of a circuit.
As a result of today's extremely large VLSI designs and complexity of tools used, there is a growing need to accurately assess the amount of layout resource required to complete a given project on a given schedule, and to track the progress. Failure to do so often results in wasted resources, missed commitments and/or excessive burdens on the design teams.
Current methods of assessing layout resource requirements involve the counting of books required to complete the design. This is a time consuming, inaccurate and inflexible process. Further, the process does not take into account the variation in difficulty of each book. It should be noted that by the term “book” it is meant the file that contains a specific schematic diagram for which a layout is to be generated. By the term “schematic” it is meant a drawing or plan that uses symbols to represent circuit patterns, including electrical connections, parts and functions. A schematic is a diagram that represents the elements of a system using abstract, graphic symbols rather than realistic pictures.
In the field of VLSI design, a schematic is used to generate a circuit layout as part of the design process. A layout is the representation of a circuit in terms of planar geometric shapes that correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of an integrated circuit. Accordingly, it becomes important to be able to accurately assess the difficulty of each layout so that use of resources and scheduling to manufacturing can be optimized.
For the above reasons, what is needed is an improved manner of assessing the amount of resources required to complete a VLSI design.